| 摘要 |
<P>PROBLEM TO BE SOLVED: To eliminate insertion of a CG cell that is not effective for reduction of power consumption regardless of a specific operation pattern. <P>SOLUTION: In the present invention, an assertion description for verifying whether insertion of a clock gating circuit into a circuit to be verified is effective for reduction of the power consumption of the circuit to be verified is generated. On the basis of the assertion description, a formal simulation for verifying the operation of the circuit to be verified is performed. On the basis of the result of the formal simulation, an insertion constraint, in which whether the clock gating circuit should be inserted into the circuit to be verified is described, is generated. <P>COPYRIGHT: (C)2013,JPO&INPIT |
