发明名称 SEMICONDUCTOR DEVICE AND WIRING LAYOUT METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing a pitch between wiring lines. <P>SOLUTION: A semiconductor device comprises a plurality of transistors formed on a semiconductor substrate, a first wiring layer equipped with first wiring lines extending in a first direction, a second wiring layer provided on an upper layer than the first wiring layer and equipped with second wiring lines extending in a second direction crossing the first direction and electrically connected with the first wiring lines, first relay wiring lines provided between the semiconductor substrate and the first wiring layer and connected to the plurality of transistors, and second relay wiring lines provided between a first relay wiring layer formed with the first relay wiring lines and the first wiring layer and each connecting the first wiring line with one of the plurality of transistors. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012222199(A) 申请公布日期 2012.11.12
申请号 JP20110087443 申请日期 2011.04.11
申请人 ELPIDA MEMORY INC 发明人 ATO HIROKAZU;NAGAMINE HISASHI
分类号 H01L27/108;H01L21/3205;H01L21/768;H01L21/82;H01L21/8242;H01L23/522 主分类号 H01L27/108
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