发明名称 |
APPARATUS AND METHOD TO HOLD PLL OUTPUT FREQUENCY WHEN INPUT CLOCK IS LOST |
摘要 |
A clock conditioning circuit including a phase detector circuit configured to provide an analog tuning signal indicative of a phase relationship between a reference clock to be conditioned and a generated clock. The controlled oscillator is configured to produce the generated clock, with the generated clock having an output frequency adjustable in response to an analog tuning signal applied to a control signal input of the controlled oscillator. Converter circuitry is provided to produce a digital representation of the analog tuning signal when the mode control circuitry is in a tracking mode. In the event the reference clock is lost, the mode control circuitry switches to a holdover mode so as to provide an analog holdover signal to the control signal input based upon the digital representations produced just prior to the loss of the reference clock.
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申请公布号 |
US2012280735(A1) |
申请公布日期 |
2012.11.08 |
申请号 |
US201113099253 |
申请日期 |
2011.05.02 |
申请人 |
ZHANG BEN-YONG;CHRISTIANSEN TOM;SCHELL CHRISTOPHER ANDREW;NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
ZHANG BEN-YONG;CHRISTIANSEN TOM;SCHELL CHRISTOPHER ANDREW |
分类号 |
H03K12/00 |
主分类号 |
H03K12/00 |
代理机构 |
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主权项 |
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地址 |
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