发明名称 BROADBAND DELTA-SIGMA ADC MODULATOR LOOP WITH DELAY COMPENSATION
摘要 An exemplary delta-sigma modulator loop applied to convert a continuous-time input signal into a discrete-time output signal. The delta-sigma modulator loop includes a conversion unit, a sampling unit, a quantization unit, a compensation unit, and a digital-to-analog converter unit. The conversion unit converts an error signal relevant to the input signal through a transfer function to generate a converted signal. The sampling unit samples the converted signal to generate a sampling signal. The quantization unit quantizes the sampling signal to obtain the output signal. The compensation unit receives the output signal and compensates a time delay of the received output signal to generate a compensation signal. The digital-to-analog converter unit is electrically coupled to the compensation unit and the conversion unit to convert the compensation signal to generate a feedback signal for regulating the error signal.
申请公布号 US2012280843(A1) 申请公布日期 2012.11.08
申请号 US201113226545 申请日期 2011.09.07
申请人 TSAI YI-LIN;LIN TSUNG-HSIEN;NATIONAL TAIWAN UNIVERSITY 发明人 TSAI YI-LIN;LIN TSUNG-HSIEN
分类号 H03M3/02;H03M1/12 主分类号 H03M3/02
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