发明名称 |
TEST PATTERN GENERATION FOR SEMICONDUCTOR INTEGRATED CIRCUIT |
摘要 |
A test pattern is sequentially selected from an original test pattern sequence constituted by a plurality of test patterns including a don't care bit. Power consumption in each of regions obtained by substantially equally dividing a layout region of a semiconductor integrated circuit in a case where a don't care value is specified in the selected test pattern and this selected test pattern is applied to the semiconductor integrated circuit is estimated. A searching is conducted for a don't care value of the selected test pattern which minimizes a variation in power consumption among the regions by repeatedly changing the don't care value and repeatedly estimating power consumption in the regions. A new test pattern sequence constituted by a plurality of test patterns including no don't care bit is generated by defining the don't care value obtained by the searching as a don't care value of the selected test pattern. |
申请公布号 |
US2012283981(A1) |
申请公布日期 |
2012.11.08 |
申请号 |
US201213550008 |
申请日期 |
2012.07.16 |
申请人 |
INOUE MICHIKO;YONEDA TOMOKAZU;SATO YASUO;KYUSHU INSTITUTE OF TECHNOLOGY;NATIONAL UNIVERSITY CORP. NARA INSTITUTE OF SCIENCE AND TECHNOLOGY |
发明人 |
INOUE MICHIKO;YONEDA TOMOKAZU;SATO YASUO |
分类号 |
G01R31/26 |
主分类号 |
G01R31/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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