| 摘要 |
The disclosure describes a processing system with a soft power switch assembly configured to include a zero-power off mode that would allow an off state with no power drain by the device while maintaining all other soft power off mode capabilities, including low power modes, (e.g., sleep, hibernation modes). The processing system can be restored from the zero-power off mode using the same actuation mechanism used when switching from a power on mode to a soft power off mode. |
