| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL-based frequency synthesizer which comes in a simple construction, yet excels in spurious response. <P>SOLUTION: A reference frequency signal to be fed into a phase comparison unit is generated based on a clock at the time a zero-cross point of a saw-tooth wave consisting of a digital signal is detected. However, the digital value in this case is a discontinous value, so that if positive and negative signs are reversed, the digital value cannot always be zero. Therefore, if, in a region where the digital value changes gradually, clock signals at which timing digital values immediately before and immediately after a zero-cross time when the positive and negative signs are reversed are read out respectively are assigned P1 and P2, and a clock signal next in timing to the clock signal P2 is assigned P3, then P1 and P3 are used at a ratio corresponding to the ratio of digital values read out at P1 and P2. <P>COPYRIGHT: (C)2013,JPO&INPIT |
