| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce glitch occurring in switching from a first clock input to a second clock input driving a clock multiplexer. <P>SOLUTION: A clock multiplexer 116 receives a first clock input and provides a clock output 118 and determines a low phase output level in the clock output in response to a low phase input level in a first clock output. For a limited period of time, a low phase output level is maintained irrespective of the phase level of the first clock input signal. The clock multiplexer 116 receives a second clock input and determines a low phase input level in the second clock input signal. Switching to providing the clock output 118 in response to the second clock input occurs during the low phase input level in the second clock input signal. Then, the output of the clock multiplexer 116 follows the phase level of the second clock signal. <P>COPYRIGHT: (C)2013,JPO&INPIT |
