发明名称 SEMICONDUCTOR MEMORY AND SYSTEM
摘要 <P>PROBLEM TO BE SOLVED: To provide a semiconductor memory and a system capable of preventing malfunction of a pseudo SRAM having a page operation function. <P>SOLUTION: A latency determination unit activates a latency extension signal when an activation of a chip enabling signal conflicts with a refresh request. A data control unit increases a reading latency during the activation of the latency extension signal as compared with that during the deactivation of the latency extension signal. The data control unit increases the reading latency during the activation of the latency extension signal as compared with that during the deactivation of the latency extension signal, and sets the difference between the reading latency for a first access request and that for a later access request during the activation of the latency extension signal to be equal to the difference between the reading latency for a first access request and that for a later access request during the deactivation of the latency extension signal. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012216283(A) 申请公布日期 2012.11.08
申请号 JP20120180133 申请日期 2012.08.15
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 FUJIOKA SHINYA
分类号 G11C11/406;G11C11/403;G11C11/407 主分类号 G11C11/406
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