发明名称 |
Gate line edge roughness reduction by using 2P/2E process together with high temperature bake |
摘要 |
A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process. |
申请公布号 |
US8304317(B2) |
申请公布日期 |
2012.11.06 |
申请号 |
US20090648802 |
申请日期 |
2009.12.29 |
申请人 |
GU YIMING;BLATCHFORD JAMES WALTER;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
GU YIMING;BLATCHFORD JAMES WALTER |
分类号 |
H01L0021/008324 |
主分类号 |
H01L0021/008324 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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