发明名称 Solder bump with inner core pillar in semiconductor package
摘要 A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.
申请公布号 US8304339(B2) 申请公布日期 2012.11.06
申请号 US201113237828 申请日期 2011.09.20
申请人 LIN YAOJIAN;STATS CHIPPAC, LTD. 发明人 LIN YAOJIAN
分类号 H01L33/62 主分类号 H01L33/62
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