发明名称 Clock and data recovery circuit
摘要 A clock and data recovery circuit includes a voltage controlled oscillator for generating an output clock according to a control voltage signal, a loop filter for outputting the control voltage signal according to a current output, a charge pump unit for outputting the current output according to an error signal, and a controller for determining a run length corresponding to input data based on the output clock from the voltage controlled oscillator. The controller further controls at least one of the voltage controlled oscillator, the loop filter and the charge pump unit according to the run length to dynamically adjust loop bandwidth. A method of adjusting loop bandwidth is also disclosed.
申请公布号 US8306175(B2) 申请公布日期 2012.11.06
申请号 US20070977984 申请日期 2007.10.26
申请人 LEE CHAO-CHENG;TZENG TZU-CHIEN;REALTEK SEMICONDUCTOR CORP. 发明人 LEE CHAO-CHENG;TZENG TZU-CHIEN
分类号 H04L7/00 主分类号 H04L7/00
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