发明名称 Memory cell with a channel buried beneath a dielectric layer
摘要 The invention provides various embodiments of a memory cell formed on a semiconductor-on-insulator (SeOI) substrate and comprising one or more FET transistors. Each FET transistor has a source region and a drain region at least portions of which are arranged in the thin layer of the SeOI substrate, a channel region in which a trench is made, and a gate region formed in the trench. Specifically, the source, drain and channel regions also have portions which are arranged also beneath the insulating layer of the SeOI substrate; the portion of channel region beneath the insulating layer extends between the portions of the source and drain regions also beneath the insulating layer; and the trench in the channel region extends into the depth of the base substrate beyond the insulating layer. Also, methods for fabricating such memory cells and memory arrays including a plurality of such memory cells.
申请公布号 US8304833(B2) 申请公布日期 2012.11.06
申请号 US20100974822 申请日期 2010.12.21
申请人 MAZURE CARLOS;FERRANT RICHARD;SOITEC 发明人 MAZURE CARLOS;FERRANT RICHARD
分类号 H04L27/12 主分类号 H04L27/12
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