发明名称 |
Strained thin body CMOS with Si:C and SiGe stressor |
摘要 |
A method is disclosed which is characterized as being process integration of raised source/drain and strained body for ultra thin planar and FinFET CMOS devices. NFET and PFET devices have their source/drain raised by selective epitaxy with in-situ p-type doped SiGe for the PFET device, and in-situ n-type doped Si:C for the NFET device. Such raised source/drains offer low parasitic resistance and they impart a strain onto the device bodies of the correct sign for respective carrier, electron or hole, mobility enhancement.
|
申请公布号 |
US2012276695(A1) |
申请公布日期 |
2012.11.01 |
申请号 |
US201113098352 |
申请日期 |
2011.04.29 |
申请人 |
CHENG KANGGUO;DORIS BRUCE B.;KHAKIFIROOZ ALI;KULKARNI PRANITA;SHAHIDI GHAVAM G.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHENG KANGGUO;DORIS BRUCE B.;KHAKIFIROOZ ALI;KULKARNI PRANITA;SHAHIDI GHAVAM G. |
分类号 |
H01L21/8238 |
主分类号 |
H01L21/8238 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|