| 摘要 |
In relation to a nonvolatile memory device having a SONOS structure according to the present invention, at least one n-well is formed on a semiconductor substrate doped with a p type dopant, and a plurality of memory cells sharing a source region are formed on the n-well. A memory array including such memory cells applies a predetermined voltage to unselected word lines and bit lines in addition to a corresponding memory cell while each memory cell is programmed, erased, and read. Thus, without introducing a related art selection gate layer, effects on adjacent memory cells are prevented, thereby preventing a reading error and program disturb. According to the present invention, a nonvolatile memory device having a SONOS structure is miniaturized, program and erase operations are possible using low power, excellent cycling characteristics are obtained, and a program erase operation is possible by means of a memory cell unit sharing the same n-well. Therefore, an erase area of a small unit may be realized. |
