| 摘要 |
Supply voltage sequencing circuitry includes a first sequencer (10-1) that produces an active level of a Power Good signal PG if a first supply voltage VOUTI exceeds an upper threshold V9o% while a control signal EN PG is active, and produces an inactive level of PG if EN PG is inactive. The PG level is latched when a control signal EN is inactive. A Power Down signal PD is produced if VOUTI is less than a lower threshold Vio% while EN is inactive. An active level of PD is produced when EN is active. A power-up sequence of supply voltages VOUTI, VOUT2, and VOUT3 monitored by the first sequencer and similar second (10-2) and third (10-3) sequencers, respectively, is determined by connection of PG of each of the first and second sequencers to control the supply voltage monitored by the next sequencer. A desired power-down sequence of the supply voltages is determined by connections of the PDs of the first and second sequencers in the power-down sequence to EN PG inputs and EN inputs of other sequencers, respectively, in accordance with a predetermined power-down algorithm. |
