发明名称 REDUCED-STRESS BUMP-ON-TRACE (BOT) STRUCTURES
摘要 The embodiments of bump-on-trace (BOT) structures and their layout on a die described reduce stresses on the dielectric layer on the metal pad and on the metal traces of the BOT structures. By orienting the axes of the metal bumps away from being parallel to the metal traces, the stresses can be reduced, which can reduce the risk of delamination of the metal traces from the substrate and the dielectric layer from the metal pad. Further, the stresses of the dielectric layer on the metal pad and on the metal traces may also be reduced by orienting the axes of the metal traces toward the center of the die. As a result, the yield can be increased.
申请公布号 US2012273934(A1) 申请公布日期 2012.11.01
申请号 US201113095185 申请日期 2011.04.27
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 SHIEH YUH CHERN;PU HAN-PING;CHEN YU-FENG;KUO TIN-HAO
分类号 H01L23/498;G06F17/50 主分类号 H01L23/498
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