发明名称 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To improve the accuracy of test of a semiconductor device (semiconductor package) in which a land for ball to be connected with a solder ball and a land for test not connected with a solder ball are provided on the undersurface of a wiring board. <P>SOLUTION: On the undersurface of a map substrate 200 used for manufacturing a lower stage side package of a POP-type semiconductor device, a plurality of lands 107 for balls and a plurality of lands 108 for test are formed. The plurality of lands 108 for test are arranged on the peripheral portion side (the side close to a dicing region DA) of the undersurface of the map substrate 200, and an Au plating layer is formed on the surface thereof by electrolytic plating. The distance (S2) between the dicing region DA and the land 108 for test placed at a position closest to the dicing region DA is larger than the diameter (DT) of the land 108 for test (S2>DT). <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012212765(A) 申请公布日期 2012.11.01
申请号 JP20110077266 申请日期 2011.03.31
申请人 RENESAS ELECTRONICS CORP 发明人 MARUYAMA KAZUYA;ISHIKAWA TOMOKAZU;KIKUCHI TAKU
分类号 H01L23/12 主分类号 H01L23/12
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