发明名称 Wafer Level Die Integration and Method
摘要 In a wafer level chip scale package (WLSCP), a semiconductor die has active circuits and contact pads formed on its active surface. A second semiconductor die is disposed over the first semiconductor die. A first redistribution layer (RDL) electrically connects the first and second semiconductor die. A third semiconductor die is disposed over the second semiconductor die. The second and third semiconductor die are attached with an adhesive. A second RDL electrically connects the first, second, and third semiconductor die. The second RDL can be a bond wire. Passivation layers isolate the RDLs and second and third semiconductor die. A plurality of solder bumps is formed on a surface of the WLSCP. The solder bumps are formed on under bump metallization which electrically connects to the RDLs. The solder bumps electrically connect to the first, second, or third semiconductor die through the first and second RDLs.
申请公布号 US2012276691(A1) 申请公布日期 2012.11.01
申请号 US201213546726 申请日期 2012.07.11
申请人 CAMACHO ZIGMUND R.;MERILO DIOSCORO A.;TAY LIONEL CHIEN HUI;DAHILIG FREDERICK R.;STATS CHIPPAC, LTD. 发明人 CAMACHO ZIGMUND R.;MERILO DIOSCORO A.;TAY LIONEL CHIEN HUI;DAHILIG FREDERICK R.
分类号 H01L21/60 主分类号 H01L21/60
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