发明名称 |
Semiconductor memory apparatus and test method thereof |
摘要 |
A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal. |
申请公布号 |
US8300496(B2) |
申请公布日期 |
2012.10.30 |
申请号 |
US20100948874 |
申请日期 |
2010.11.18 |
申请人 |
YUN TAE SIK;LEE HYUNG DONG;CHOI JUN GI;BYEON SANG JIN;SHIN SANG HOON;SK HYNIX INC. |
发明人 |
YUN TAE SIK;LEE HYUNG DONG;CHOI JUN GI;BYEON SANG JIN;SHIN SANG HOON |
分类号 |
G11C8/18;G11C7/00;G11C8/16 |
主分类号 |
G11C8/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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