发明名称 Memory system and method for providing error correction
摘要 An error correction decoder includes a syndrome computation circuit, an error correction and computation circuit and an error correction circuit. The syndrome computation circuit calculates a syndrome of read data. The error correction and computation circuit calculates a location of a single-bit error using a division operation between elements of the syndrome when the single-bit error exists in the read data. The error correction circuit corrects the single-bit error of the read data based on the location of the single-bit error.
申请公布号 US8301986(B2) 申请公布日期 2012.10.30
申请号 US20090390700 申请日期 2009.02.23
申请人 JO NAM-PHIL;YOUN DAE-HAN;SAMSUNG ELECTRONICS CO., LTD. 发明人 JO NAM-PHIL;YOUN DAE-HAN
分类号 H03M13/00 主分类号 H03M13/00
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