发明名称 |
Programmable compute unit with internal register and bit FIFO for executing Viterbi code |
摘要 |
A programmable compute unit with an internal register with a bit FIFO for executing Viterbi code is configured to accumulate in the forward path the best-path to each state in an internal register and store the survivor trace back information bit for each state in each stage in a bit FIFO; and in the trace back, selecting the optimal best-path through the Viterbi trellis by tracing through the bit trace back information survivor bits beginning with the survivor bit of the last stage path; and generating in response to the Viterbi constrain length and a current bit FIFO address, the next bit FIFO address and decoded output bit for the next previous stage. |
申请公布号 |
US8301990(B2) |
申请公布日期 |
2012.10.30 |
申请号 |
US20070904341 |
申请日期 |
2007.09.27 |
申请人 |
WILSON JAMES;STEIN YOSEF;YUKNA GREGORY;LAHR LEWIS;ANALOG DEVICES, INC. |
发明人 |
WILSON JAMES;STEIN YOSEF;YUKNA GREGORY;LAHR LEWIS |
分类号 |
H03M13/03 |
主分类号 |
H03M13/03 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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