发明名称 |
Timing recovery circuit, communication node, network system, and electronic device |
摘要 |
A comparison period determiner (110) detects whether or not a change occurs in received data during a comparison period including a timing at which a rising edge of a reference clock occurs. A phase determiner (120) determines whether a rising edge of the received data is located before or after the reference clock and determines whether a falling edge of the received data is located before or after the reference clock, and outputs a first determination signal and a second determination signal indicating results of the respective determinations. A synchronous data generator (130) outputs a signal having a level depending on a result of the detection by the comparison period determiner (110) and an output of the phase determiner (120), as synchronous data, in synchronization with a synchronization clock. |
申请公布号 |
US8300755(B2) |
申请公布日期 |
2012.10.30 |
申请号 |
US20070602751 |
申请日期 |
2007.11.30 |
申请人 |
ARIMA YUKIO;PANASONIC CORPORATION |
发明人 |
ARIMA YUKIO |
分类号 |
H04L7/00 |
主分类号 |
H04L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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