发明名称 Specialized processing block for programmable logic device
摘要 A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for performing floating point operations. The floating point circuitry preferably includes rounding and normalization circuitry. To perform mantissa multiplications, the floating point circuitry preferably relies on the aforementioned multipliers of the specialized processing block.
申请公布号 US8301681(B1) 申请公布日期 2012.10.30
申请号 US20060447474 申请日期 2006.06.05
申请人 LEE KWAN YEE MARTIN;LANGHAMMER MARTIN;NGUYEN TRIET M.;LIN YI-WEN;ALTERA CORPORATION 发明人 LEE KWAN YEE MARTIN;LANGHAMMER MARTIN;NGUYEN TRIET M.;LIN YI-WEN
分类号 G06F7/38;G06F7/00;G06F15/00 主分类号 G06F7/38
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