| 摘要 |
A memory access controller including a command analysis unit to receive write access request and command data and to analyze access to a memory, a command execution unit to output command and data control signals to the memory based on write data, and the analysis result, a mode setting unit to switch between a first operation mode in which a write access request is issued when both the command data and the corresponding write data are available, and a second operation mode in which a write access request is issued when the command data is available independently of availability of the write data corresponding to the command data, and a timing arbitration unit provided for each bus master to output the write access request and command data to the command analysis unit and output the write data to the command execution unit in accordance with the mode setting unit. |
