发明名称 |
Programmable packet processor with flow resolution logic |
摘要 |
A programmable packet switching controller has a packet buffer, a programmable packet classification engine and an application engine. The packet buffer stores inbound packets, and includes a header data extractor to extract header data from the inbound packets and store the extracted header data in a header data cache. The header data extractor also generates a header data cache index and provides it to the packet classification engine for it to retrieve the extracted header data. The application engine has a number of programmable sub-engines arrayed in a pipelined architecture. The packet classification engine provides start indicators based on the packet classification to the programmable sub-engines to identify application programs to be executed.
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申请公布号 |
US8300534(B2) |
申请公布日期 |
2012.10.30 |
申请号 |
US20100706687 |
申请日期 |
2010.02.16 |
申请人 |
CATHEY JIM;MICHELS TIMOTHY S.;ALCATEL LUCENT |
发明人 |
CATHEY JIM;MICHELS TIMOTHY S. |
分类号 |
G06F9/00;H04L12/28;H04L12/56;H04L29/06 |
主分类号 |
G06F9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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