| 摘要 |
Device features, such as gate lengths and channel widths, are selectively altered by first identifying those devices within a semiconductor die that exhibit physical attributes, e.g., leakage current and threshold voltage magnitude, that are different than previously verified by a design/simulation tool used to design the devices. The identified, non-conforming devices are then further identified by the amount of deviation from the original design goal that is exhibited by each non-conforming device. The non-conforming devices are then mathematically categorized into bins, where each bin is tagged with a magnitude of deviation from a design goal. The mask layers defining the features of the non-conforming devices are then selectively modified by an amount that is commensurate with the tagged deviation. The selectively modified mask layers are then used to generate a new semiconductor die that exhibits improved performance. |
