发明名称 |
Receiving circuit and sampling clock control method |
摘要 |
A receiving circuit includes: a clock generating circuit to generate a plurality of clock signals in a cycle; an oversampling circuit to oversample input data based on the plurality of clock signals and output a plurality of samples of digital data in a unit interval; a data boundary determining circuit to detect a changing point of the digital data, determine data boundaries of the unit interval based on the changing point, and output digital data corresponding to a central data between the data boundaries; and a clock phase control circuit to control a phase of at least one of the plurality of clock signals so that a first number of the plurality of samples becomes a certain value when a second number of samples between the data boundaries is larger than a threshold value. |
申请公布号 |
US8299948(B2) |
申请公布日期 |
2012.10.30 |
申请号 |
US201113023765 |
申请日期 |
2011.02.09 |
申请人 |
SHIBASAKI TAKAYUKI;KIBUNE MASAYA;YAMAMOTO TAKUJI;FUJITSU LIMITED |
发明人 |
SHIBASAKI TAKAYUKI;KIBUNE MASAYA;YAMAMOTO TAKUJI |
分类号 |
H03M1/12 |
主分类号 |
H03M1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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