A DIGITAL DELAY-LOCKED LOOP USING A HYBRID SEARCH ALGORITHM AND METHOD FOR CONTROLLING THE SAME

摘要

PURPOSE: A digital delay locked loop circuit using a hybrid search algorithm and a control method thereof are provided to obtain a wide operation frequency range and high delay resolution using the hybrid search algorithm. CONSTITUTION: A first delay locked loop(100) eliminates a phase error of an output clock signal and an input clock signal to be within predetermined delay resolution. The first delay locked loop applies binary searching using a variable successive approximation register during an output digital bit generating process to eliminate a phase error. A second delay locked loop(200) is arranged in the backend of the first delay locked loop. The second delay locked loop eliminates the phase error of the output clock signal and the input clock signal to be within the predetermined delay resolution by receiving the output signal of the first delay locked loop. The second delay locked loop applies a sequential search method using a counter during the output digital bit generating process to eliminate the phase error. [Reference numerals] (100) Coarse loop; (110) Digital control delay line; (120) Phase interpolation range selector; (130) 5 to 32 thermometer decoder; (140) 2 to 3 thermometer decoder; (140) Control part; (150) Variable continuous approximation register; (160) First phase detector; (200) Fine loop; (210) Phase interpolator; (220) Convertor; (230) Digital-analog convertor; (240) Counter; (250) Second phase detector