A ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE
摘要
<p>A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.</p>
