发明名称 |
Method and Apparatus for Circuit Partitioning and Trace Assignment in Circuit Design |
摘要 |
Methods and apparatuses for designing at least one integrated circuit (IC). In one embodiment, the method comprises partitioning a circuit into portions that represent a partitioning solution and assigning traces to interconnect the portions to generate a trace assignment solution. The method further comprises optimizing the circuit through a modification of at least one of the partitioning solution and the trace assignment solution, the optimizing based on evaluating a design parameter which is based at least in part on the trace assignment solution.
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申请公布号 |
US2012272199(A1) |
申请公布日期 |
2012.10.25 |
申请号 |
US201213465930 |
申请日期 |
2012.05.07 |
申请人 |
PANDEY AWARTIKA;BORKOVIC DRAZEN;MCELVAIN KENNETH S. |
发明人 |
PANDEY AWARTIKA;BORKOVIC DRAZEN;MCELVAIN KENNETH S. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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