发明名称 DYNAMIC LOCKSTEP CACHE MEMORY REPLACEMENT LOGIC
摘要 To facilitate dynamic lockstep support, replacement states and/or logic used to select particular cache lines for replacement with new allocations in accord with replacement algorithms or strategies may be enhanced to provide generally independent replacement contexts for use in respective lockstep and performance modes. In some cases, replacement logic that may be otherwise conventional in its selection of cache lines for new allocations in accord with a first-in, first-out (FIFO), round-robin, random, least recently used (LRU), pseudo LRU, or other replacement algorithm/strategy is at least partially replicated to provide lockstep and performance instances that respectively cover lockstep and performance partitions of a cache. In some cases, a unified instance of replacement logic may be reinitialized with appropriate states at (or coincident with) transitions between performance and lockstep modes of operation.
申请公布号 US2012272006(A1) 申请公布日期 2012.10.25
申请号 US201113090056 申请日期 2011.04.19
申请人 MOYER WILLIAM C.;FREESCALE SEMICONDUCTOR, INC. 发明人 MOYER WILLIAM C.
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
主权项
地址