Controlled value reference signal of resistance based memory circuit

摘要

A memory circuit comprises a magnetoresistive random access memory MRAM reference bit cell comprising a first current clamp and a first load circuit. The reference bit cell receives a control input at a control terminal of the first current clamp and outputs, in response to the control input, a controlled value reference voltage. The memory circuit also comprises a magnetoresistive random access memory MRAM data bit cell comprising a second load circuit, an MRAM load generator cell for generating a load control signal, the load control signal being supplied to the first load circuit and the second load circuit, and a sense amplifier. The sense amplifier comprises a first input coupled to the at least one magnetoresistive random access memory MRAM bit cell and a second input adapted to receive an input signal comprising the controlled value reference voltage.