| 摘要 |
The circuit has a q-input carry-save adder (CSA), and a set of multiplexers (10) that is arranged for an input of the adder. The multiplexers are arranged with four K-bit channels receiving a value 0. Each multiplexer has a set of channel selection inputs. A set of bits of a q-bit operand is supplied to the selection inputs. A set of bits of another q-bit operand is supplied to other selection inputs of the multiplexer. |
