| 摘要 |
Provided is a register circuit including a timing circuit controlled by an external control signal to receive an external timing signal and then to transmit a first timing signal and a second timing signal, wherein the first timing signal and the second timing signal have phases inverse to each other; two pass gates controlled by the first timing signal and the second timing signal to receive starting pulse signals and then transmit the pulse signals as one of the pass gates turns on; a signal output unit receiving the pulse signals to transmit an output signal; and two switches controlled by the external control signal to receive and to transmit the output signal as one of the switches turns on. |
