Clock de-skewing delay locked loop circuit

摘要

A clock de-skewing delay locked loop circuit is revealed. In the clock de-skewing delay locked loop circuit, a timing control circuit generates a first and a second clock signals according to an external and an internal clock signal. A clock delay line delays the first clock signal or the external clock signal to generate delay signals. A delay mirror circuit synchronizes the internal clock signal with the external clock signal. A phase adjustment circuit inverts the internal clock signal according to the phase difference. An inverting buffer circuit buffers the external clock signal or the first clock signal for adding an initial delay time so as to make a duty cycle of internal clock signal and of the external clock signal complement each other. Thus the duty cycle of the external clock signal in the proposed circuit is not necessarily 50%.