发明名称 |
Reliability evaluation circuit and reliability evaluation system |
摘要 |
A reliability evaluation system comprises a reliability evaluation circuit and a reliability evaluation control circuit. The reliability evaluation circuit includes a stress device array and a stress voltage generating block configured to receive a control voltage, generate stress voltages generated by using two reference voltages, and apply the stress voltages to the unit devices in a stress mode via first I/O lines according to the control voltage. The stress device array includes the unit devices that are matrix-arrayed. Each of the unit devices has a first terminal connected to one of the first I/O lines and a second terminal connected to one of second I/O lines. The reliability evaluation control circuit is configured to generate the control voltage and the two reference voltages, and test reliability of the unit devices by using the first I/O lines and the second I/O lines. |
申请公布号 |
US8294472(B2) |
申请公布日期 |
2012.10.23 |
申请号 |
US20100659444 |
申请日期 |
2010.03.09 |
申请人 |
KWON SANG-JIN;LEE JAE-HOON;KANG YONG-HA;LEE JONG-WON;SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KWON SANG-JIN;LEE JAE-HOON;KANG YONG-HA;LEE JONG-WON |
分类号 |
G01R31/02;G01R31/26 |
主分类号 |
G01R31/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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