发明名称 |
Multilayer pillar for reduced stress interconnect and method of making same |
摘要 |
A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
|
申请公布号 |
US8293587(B2) |
申请公布日期 |
2012.10.23 |
申请号 |
US20070870583 |
申请日期 |
2007.10.11 |
申请人 |
JADHAV VIRENDRA R;SEMKOW KRYSTYNA W;SRIVASTAVA KAMALESH K;SUNDLOF BRIAN R;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
JADHAV VIRENDRA R;SEMKOW KRYSTYNA W;SRIVASTAVA KAMALESH K;SUNDLOF BRIAN R |
分类号 |
H01L21/00 |
主分类号 |
H01L21/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|