发明名称 |
Method and apparatus for performing static analysis optimization in a design verification system |
摘要 |
Method and apparatus for performing static analysis optimization in a design verification system is described. In one example, a description of a verification environment having constrained objects is obtained. The constrained objects are analyzed incrementally to create a data structure of nodes. Each node includes a description of variables transitively connected by constraints. At least one of the nodes reuses a description from at least one other node. The data structure is then used during logic design verification. |
申请公布号 |
US8296697(B2) |
申请公布日期 |
2012.10.23 |
申请号 |
US20070725288 |
申请日期 |
2007.03.19 |
申请人 |
GAL AMIT;UZIEL SHLOMI;NOY AMOS;CADENCE DESIGN SYSTEMS, INC. |
发明人 |
GAL AMIT;UZIEL SHLOMI;NOY AMOS |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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