| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same, which can achieve high capacity and area reduction of a capacitor. <P>SOLUTION: An EEPROM memory cell 50 includes an N<SP POS="POST">-</SP>layer 21a, a tunnel insulation film 13a, a floating gate electrode 15a, an inter-electrode insulation film 17a and a control gate electrode 19a, which are provided on a memory cell region of a silicon substrate 1. A capacitor 60 includes a lower electrode layer 24a, a first dielectric film 13c, a common electrode 15c, a second dielectric film 17c and an upper electrode 19c, which are provided on a capacitor region of the silicon substrate 1. The lower electrode layer 24a, the first dielectric film 13c and the common electrode 15c constitute a first capacitor 61. The common electrode 15c, the second dielectric film 17c and the upper electrode 19c constitute a second capacitor 62. The first capacitor 61 and the second capacitor 62 are connected in parallel. <P>COPYRIGHT: (C)2013,JPO&INPIT |
