发明名称 CLOCK DUTY CORRECTION CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a clock duty correction circuit that corrects a clock signal with a constant duty without causing an output clock signal to oscillate. <P>SOLUTION: A clock duty correction circuit 100 includes: a one-shot pulse signal generation section 110 for receiving an input clock signal to generate a one-shot pulse signal having a waveform rising in phase with the waveform of the input clock signal and having a constant pulse width; a NOR circuit 120 into one input side of which an output of the one-shot pulse signal generation section 110 is input; a feedback circuit 140 which has a first delay circuit 130 for delaying an output signal of the NOR circuit 120, and feeds back the output of the NOR circuit 120 delayed by the first delay circuit 130 to the other input side of the NOR circuit 120; and a second low pass filter 150 into which the output signal of the NOR circuit 120 is input. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012199748(A) 申请公布日期 2012.10.18
申请号 JP20110062124 申请日期 2011.03.22
申请人 KYOCERA CORP 发明人 TANAKA KENSAKU;ITO TAKASHI
分类号 H03K5/05 主分类号 H03K5/05
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