发明名称 |
METHOD AND APPARATUS FOR LOW-PIN-COUNT SCAN COMPRESSION |
摘要 |
A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step. |
申请公布号 |
US2012266036(A1) |
申请公布日期 |
2012.10.18 |
申请号 |
US201213529686 |
申请日期 |
2012.06.21 |
申请人 |
TOUBA NUR A.;WANG LAUNG-TERNG;JIANG ZHIGANG;WU SHIANLING;YAN JIANPING;SYNTEST TECHNOLOGIES, INC. |
发明人 |
TOUBA NUR A.;WANG LAUNG-TERNG;JIANG ZHIGANG;WU SHIANLING;YAN JIANPING |
分类号 |
G01R31/3177;G06F11/25 |
主分类号 |
G01R31/3177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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