发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE MANUFACTURING METHOD
摘要 <P>PROBLEM TO BE SOLVED: To solve problems of low oxidation resistance and low wet etching resistance caused by use of a High-k insulation film and a metal electrode component as a gate stack material; the problems being caused because though it is important to reduce a distance between end parts of adjacent gates for microfabrication of a pattern, particularly in order to reduce a cell area of SRAM, it is hard in general to transfer a pattern in a single exposure by ArF in a 28 nm technology node, and accordingly, a microfabricated pattern is formed by repetition of exposure, etching, and the like a plurality of times. <P>SOLUTION: According to the present invention, in patterning of a multilayer gate film having a high-k gate insulation film and a metal electrode film in a memory region, first, etching of a cutting region between adjacent gate electrodes is performed by using a first resist film, and after the unnecessary first resist film is removed, etching of a line-and-space pattern by using a second resist film is performed. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012199361(A) 申请公布日期 2012.10.18
申请号 JP20110062138 申请日期 2011.03.22
申请人 RENESAS ELECTRONICS CORP 发明人 SHINOHARA MASAAKI
分类号 H01L27/10;G03F7/26;H01L21/28;H01L21/3065;H01L21/3213;H01L21/768;H01L21/8242;H01L21/8244;H01L21/8247;H01L27/108;H01L27/11;H01L27/115;H01L29/423;H01L29/49 主分类号 H01L27/10
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