发明名称 MULTITHREADED PROCESSOR WITH MULTIPLE CONCURRENT PIPELINES PER THREAD
摘要 <p>A multithreaded processor with a multithreaded instruction cache and means for accessing a register file associated with the instruction cache via a thread identifier for the thread. The register file includes a data operand and an address operand, and the register file includes a plurality of thread identifiers for a plurality of threads.</p>
申请公布号 KR20120115553(A) 申请公布日期 2012.10.18
申请号 KR20127022423 申请日期 2005.04.07
申请人 ASPEN ACQUISITION CORPORATION 发明人 HOKENEK ERDEM;MOUDGILL MAYAN;SCHULTE MICHAEL J.;GLOSSNER C. JOHN
分类号 G06F9/30;G06F9/38;G06F15/00 主分类号 G06F9/30
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