发明名称 LAYOUT METHOD OF INTEGRATED CIRCUIT DEVICE, LAYOUT DEVICE, PROGRAM AND INFORMATION STORAGE MEDIUM
摘要 <P>PROBLEM TO BE SOLVED: To provide a layout method of an integrated circuit device that allows a layout design of the integrated circuit device to be executed with less man-hours and in a short period of time, and further to provide a layout device, a program, an information storage medium and the like. <P>SOLUTION: A layout method of an integrated circuit device using macro-cells includes: an overlapping detection step for detecting an overlapping between a first macro-cell of which a disposing position can be changed or first power supply wiring of the first macro-cell and second power supply wiring disposed on a chip; and a power supply wiring replacement step for replacing the first power supply wiring and the second power supply wiring with shared power supply wiring when the overlapping therebetween is detected in the overlapping detection step. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012198854(A) 申请公布日期 2012.10.18
申请号 JP20110064037 申请日期 2011.03.23
申请人 SEIKO EPSON CORP 发明人 YAMADA YOICHI
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04 主分类号 G06F17/50
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