| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the TAT for LogicBIST analysis. <P>SOLUTION: A semiconductor integrated circuit of the present invention comprises: a plurality of MISR circuits M1, M2, and M3; and a plurality of scan chain groups F1, F2, and F3 which are connected so as to correspond to the plurality of MISR circuits M1, M2, and M3. In a first mode, the plurality of MISR circuits M1, M2, and M3 function as a MISR circuit performing a compression operation for signals output from the plurality of scan chain groups F1, F2, and F3. In a second mode, each of the plurality of MISR circuits M1, M2, and M3 functions as a MISR circuit performing a compression operation for individual output from each of the plurality of scan chain groups F1, F2, and F3. <P>COPYRIGHT: (C)2013,JPO&INPIT |
