发明名称 |
MULTIPLE-PHASE CLOCK GENERATOR |
摘要 |
A multiple-phase clock generator includes at least one stage of dividers. A clock signal is supplied as a first stage clock input to dividers in a first stage of dividers. An N-th stage includes 2N dividers, where N is a positive integer number. Each divider in the first stage is configured to divide a first clock frequency of the first stage clock input by 2 to provide a first stage output. Each divider in the N-th stage is configured to divide an N-th clock frequency of an N-th stage clock input by 2 to provide an N-th stage output. The N-th stage outputs from the dividers in the N-th stage provide 2N-phase clock signals that are equally distributed with a same phase difference between adjacent phase clock signals. |
申请公布号 |
US2012262212(A1) |
申请公布日期 |
2012.10.18 |
申请号 |
US201113084817 |
申请日期 |
2011.04.12 |
申请人 |
LIN CHIH-CHANG;CHERN CHAN-HONG;HUANG MING-CHIEH;CHUNG TAO WEN;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
LIN CHIH-CHANG;CHERN CHAN-HONG;HUANG MING-CHIEH;CHUNG TAO WEN |
分类号 |
H03K5/15 |
主分类号 |
H03K5/15 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|