| 摘要 |
Data processing apparatus comprises processing circuitry 50, 60, a scalar register bank 10 and a vector register bank 40 and decoding circuitry 70. The decoding circuitry is arranged to decode a sequence of instructions to generate control signals for the processing circuitry, such that the operations performed by the processing circuitry are dictated by the sequence of instructions. A decode modifier instruction within the sequence of instructions will alter decoding of a subsequent scalar instruction in the sequence by mapping scalar operand(s) specified by the subsequent scalar instruction to vector operand(s) in the vector register bank, and determining, in dependence on the scalar operation specified by the subsequent scalar instruction, a vector operation to be performed on at least a subset of the operand elements within the at least the one vector operand. This removes the need to individually define separate vector instructions for those vector operations, alleviating the pressure on instruction encoding space with a fixed size instruction set. |
