发明名称 Semiconductor memory device capable of suppressing peak current
摘要 A memory cell array includes a plurality of memory cells, in which n (n is a natural number equal to 3 or larger) cells are simultaneously written. A control circuit controls the memory cell array. A conversion circuit converts data constituted of k (k is equal to n or smaller, and is a natural number equal to 3 or larger) bits stored in the memory cells into data of h (h is equal to k or larger, and is a natural number equal to 2 or larger) bits on the basis of a conversion rule.
申请公布号 US8289783(B2) 申请公布日期 2012.10.16
申请号 US20100948256 申请日期 2010.11.17
申请人 SHIBATA NOBORU;KABUSHIKI KAISHA TOSHIBA 发明人 SHIBATA NOBORU
分类号 G11C11/34;G11C16/04 主分类号 G11C11/34
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