发明名称 |
Overlay vernier key and method for fabricating the same |
摘要 |
Methods are disclosed for fabricating an overlay vernier key. A method includes forming a pattern layer and an insulating layer over a semiconductor substrate. The insulating layer is etched to form insulating layer patterns to partially expose the pattern layer. Spacers are formed on sidewalls of the insulating layer patterns. The insulating layer patterns are removed while leaving the spacers to obtain a spacer-shaped etch mask. The pattern layer is etched using the spacer-shaped etch mask to form vernier patterns. At least one of the vernier patterns has a hollow shape. |
申请公布号 |
US8288242(B2) |
申请公布日期 |
2012.10.16 |
申请号 |
US201113211197 |
申请日期 |
2011.08.16 |
申请人 |
CHO BYEONG HO;KO SUNG WOO;HYNIX SEMICONDUCTOR INC. |
发明人 |
CHO BYEONG HO;KO SUNG WOO |
分类号 |
H01L21/76 |
主分类号 |
H01L21/76 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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